A modification to a standard PCI data bus arrangement for driving a high speed printer to allow a higher data rate by providing an additional bus memory, and its I/O, on the bus to serve as an intermediary between the main CPU memory and the I/O ports connected to the printer.
The industry standard PCI (Personal Computer Interconnection) bus will connect a computer to the other application boards in the system. The computer contains a CPU, main memory and cache, among other things, all connected to the bus through an interface chip comprising a FIFO, all standard off-the-shelf components. In a "postwrite" transfer from any component on the PCI bus to the main memory, the component posts the address into which the data is to be written, and loads the data into the FIFO. The component can then go on with another activity, assuming that the data will eventually be DMA loaded into main memory. In a "-read" or "pre-fetch", the component must first specify the address in the memory from which the data must come, and then wait until the data is available from the FIFO. To speed up the process, in a "pre-fetch", if the computer knows what data the component will need, the FIFO can be loaded in advance.
To drive a high speed color printer which prints four color separations, there must be four I/O ports which transport data at high rates from the computer main memory to the printer through a FIFO register in the interface chip, and this single FIFO, along with the demands made by the CPU and the memory protocol, limits the throughput. The chip set could be modified to have an additional FIFO for each printer color separation. However, the entire computer chip set is an industry standard, so modification of the chip set is not an alternative. The question, then, is how to modify the system to allow a higher data throughput.